Detectors (XSD-DET)

 

 

The mission of the XSD Detectors Group is to deliver cutting-edge detectors to APS beamlines. Our mission is accomplished in two ways.

First, we introduce new, cutting-edge commercial detectors to the APS community via the Detector Pool. We accelerate and facilitate early access to new detectors on the market. We also provide technical detector advisory services in a variety of ways (e.g., market research, design reviews, etc.) to assist beamlines with detector purchases and best detector practices.

Second, we develop new, cutting-edge detectors which are unlikely to be commercially available. The group is engaged in a number of detector R&D projects to meet the future needs of the APS. The current initiatives include germanium strip detectors, pixel array detectors, and superconducting Transition Edge Sensor (TES) detectors. Each development is linked to scientific strategic goals of the APS, as well as leveraging local resources. This serves to provide a well-balanced R&D portfolio for the group.

The XSD Detectors strategy and goals document can be found here: (pdf).

Detector Pool

Detector Pool Vortex ME4

The XSD Detector Pool provides on-call technical support, expertise, and guidance on detectors at the APS. This is accomplished in a number of ways.

The Detector Pool supports a wide range of commercially available detectors and an assortment of electronics. Typically, these are more expensive detectors (e.g., Pilatus, Eiger, Vortex ME-4) where individual beamlines cannot afford or justify dedicated systems. By facilitating access to these expensive detectors through time-sharing, we make very efficient use of resources. We also provide back-up support (i.e., drop-in spares) for dedicated beamline detectors in case of catastrophic failures.

The Detector Pool serves as the outlet to introduce new, cutting-edge commercial detectors to the entire APS community. We accelerate and facilitate early access to new and upgraded detectors that come on the market (e.g., GE a-Si flat panels, Vortex ME-4, Pilatus, Pixirad CdTe, Eiger). Detectors can be requested below.

Submit a Detector Pool Request

If you have never requested a detector before, please contact [email protected] to have your name added to the database.

Detector Pool staff can be contacted during normal work hours / run period Monday-Friday at 2-9490 or for general questions [email protected]

Detector Pool documentation can be found here: Detector Pool Box Folder (Requires ANL domain account)

The Detector Pool Feedback Form can be found here: Feedback

Detector R&D

 

To complement the Detector Pool, the group pursues R&D activities aimed at enabling unique detector capabilities not commercially available. These projects were chosen to align with the major scientific thrusts of the APS, take advantage of the source, leverage strategic partnerships with US domestic detector groups and utilize unique Argonne facilities (e.g. CNM Cleanroom).

We currently focus our detector R&D efforts in three areas: germanium strip detectors, pixel array detectors and superconducting TES detectors.

Germanium Strip Detectors: We are collaborating closely with the NSLS-2 detector group on the Germanium strip detector for high-energy spectroscopic applications.

Pixel Array Detectors: We are collaborating closely with Cornell on the MM-PAD detector and with BNL and FNL on the VIPIC detector for ultra-fast XPCS.

TES Detectors: We are collaborating closely with NIST on TES for high energy-resolution emission detection applications. At the APS, we are focused on developing application-specific TES sensors for hard X-ray applications. In particular, we are modeling, designing, fabricating and testing TES sensors optimized for XES, XRF, XAFS and Compton scattering experiments. An LDRD-funded TES detector for 1-BM will be deployed in 2021.

Finally, we are exploring several new initiatives including refractive X-ray lenses using deep silicon etching, nano-calorimeters/bolometers for low temperature heat capacity sample measurements and X-ray detection and ASICs with on-chip compression.